This invention relates to a protective covering for an electronic package and, more particularly, to a dielectric protective covering for an electronic package comprising a semiconductor chip, a substrate, and conductors which may be used within an information handling system (computer).
There have been previous attempts to apply coatings onto electronic packages, including attempts to encapsulate chips and conductors with the main emphasis of providing mechanical strength to the conductors. However, such efforts have not typically solved problems associated with moisture sensitivity.
In electronic chip carrier packages, moisture can cause various problems such as delamination, corrosion, formation of plated fiber shorts, chip cracking and debonding. This may result in yield loss and/or functional failure during assembly and reliability testing. Organic packages are particularly susceptible to moisture due to the hydrophilic nature of resins such as epoxies and polyimides when exposed to moisture, and are susceptible to the brittleness of glass reinforcement interfaces.
U.S. Pat. No. 5,474,957 to Urushima shows a process for building/assembling a chip onto a flexible film member. The assembly process involves using a piece of resin, to encapsulate the wire bond leads and act to hold the chip to the film. While the purpose of this resin is in part to prevent corrosion/oxidation, and to mechanically protect the wire bond leads, it is used in an entirely different location and with a completely different purpose than the present invention. U.S. Pat. No. 5,474,957 describes the use of a wire bond encapsulant which is applied only to the wire bond area. The present invention, on the other hand, involves using a protective coating over substantially the entire assembled package including, chip, wires (if used), or solder joints and the chip carrier.
U.S. Pat. No. 5,436,203 to Lin covers the concept of building an EMI shielded chip carrier package by shielding the chip and wire bonds. The bottom is shielded with a buried power plane or reference plane, and the top is shielded with a conductive encapsulate. The two shielding layers are electrically connected via plated thru holes. The chip and wire bonds are first covered with a non conductive encapsulant. Lin is different from the present invention for substantially the same reasons as Urushima above.
U.S. Pat. No. 5,496,775 to Brooks discloses using stacked and bonded metal balls as the electrical connection points. The chip is enclosed in an encapsulation material. The primary function of the encapsulant material appears to be to provide mechanical support for the chip and ball towers. The encapsulation is performed in two steps. First, a layer of encapsulant is formed within a mold or cavity. Next, the ball stacked chip is placed in the cavity and additional encapsulant is flooded into the mold and around the stacked ball towers. These two encapsulant layers form part of the chip package. The primary subject covered by Brooks appears to be the concept of using stacked metal balls as electrical leads, with the primary purpose of the encapsulant layer being to support and strengthen these leads.
U.S. Pat. No. 4,351,101 to Young shows a method of making connection to CCD (charged coupled device) chips. The method describes how metal pads are allowed to sink through a layer of uncured epoxy, via gravity, as an improvement over the previous method which involved hours of lapping (mechanical sanding).
U.S. Pat. No. 2,720,617 to Sardella covers a method of making a two-part case for early transistor packages, (circa 1955). The case consists of two pieces of TEFLON, (or other fluorocarbons), which are mechanically machined to form a hollow tube and a plug, both threaded. TEFLON is a trademark of E. I. du Pont de Nemours and Co., Inc. The transistor is placed into the tube, the tube is filled with epoxy encapsulant and the plug is screwed into the tube. The transistors are covered for improved resistance to vibration, moisture and mechanical damage.
The glasses used in electronic packaging of semiconductor and other electronic devices may successfully provide hermetic packaging; however, such glasses may create problems. Conventional sealing glasses are usually brittle and glass sealed semiconductor packages require special care in handling both during and subsequent to processing. This is necessary to avoid fracture of the glass and resulting loss of package hermeticity. The methods of applying the glass to the components to be sealed are also generally somewhat tedious and costly. One known method of applying the glass is to mix finely powdered glass with a suitable vehicle. The mixture is then silk screened in place upon the components. Next, the glass applied component is fired to coalesce the individual glass particles into a continuous glass coating in the areas previously silk screened. At the same time, any residue from the vehicle used during silk screening is driven off.
The present invention comprises a product (electronic package) and a method for making said product, that contains a semiconductor chip wherein substantially the entire electronic package is encapsulated with a solution which forms a protective coating sufficient to protect the electronic package from exposure to moisture and other adverse environmental conditions.
It is an object of the present invention to enhance the art of information handling systems. More particularly, it is an object of the present invention to provide an improved method for mass producing electronic packages. Further, it is an object of the present invention to provide an improved electronic package product.
In one aspect of the invention, there is provided a method of providing a protective covering on an electronic package including a substrate, a semiconductor chip positioned and electrically coupled to the substrate, and a plurality of conductors on the substrate for electrically connecting the substrate to an external substrate. The method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering.
In accordance with another aspect of the invention, there is provided a method of providing a protective covering on an electronic package including a substrate, a semiconductor chip positioned on and electrically coupled to the substrate, and a plurality of conductors on the substrate for electrically coupling the substrate to an external substrate. In this aspect of the invention, substantially all of the external surfaces of the substrate, the semiconductor chip and the plurality of conductors are initially covered with the protective covering. Thereafter, a portion of the covering is removed from a portion of the external surfaces of the plurality of conductors.
According to another aspect of the invention, there is provided an electronic package comprising a first substrate, a semiconductor chip positioned on a first surface of the first substrate and electrically coupled to the substrate, a plurality of conductors located on a second surface of the first substrate for electrically coupling the first substrate to an external substrate, and a dielectric protective covering, substantially covering all of the external surfaces of the electronic package, except for a portion of the plurality of conductors.
According to yet another aspect of the invention, there is provided an electronic package comprising a substrate having first and second surfaces, a semiconductor chip positioned on the first surface of the substrate and electrically coupled to the substrate, a plurality of conductors located on the second surface of the substrate for electrically coupling the substrate to an external substrate, and a dielectric protective covering, substantially covering the entire external surfaces of the electronic package.